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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. 00a 02/01/08 is62c51216al is65c51216al copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. 512k x 16 low voltage, ultra low power cmos static ram features ? high-speed access time: 45ns, 55ns ? cmos low power operation C 36 mw (typical) operating C 12 w (typical) cmos standby ? ttl compatible interface levels ? single power supply C 4.5v--5.5v v d d ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? automotive temperature (-40 o c to +125 o c) ? lead-free available description the issi is62c51216al and is65c51216al are high- speed, 8m bit static rams organized as 512k words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low , cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte (lb) access. the is62c51216al and is65c51216al are packaged in the jedec standard 48-pin mini bga (9mm x 11mm) and 44-pin tsop (type ii). functional block diagram advanced information february 2008 a0-a18 cs1 oe we 512k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb cs2
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00a 02/01/08 is62c51216al, is65c51216al pin configurations 48-pin mini bga (9mmx11mm) pin descriptions a0-a18 address inputs i/o0-i/o15 data inputs/outputs cs1, cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v d d power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 v dd` v dd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 a18 a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 a18 a8 a9 a10 a11 a17 44-pin tsop (type ii)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. 00a 02/01/08 is62c51216al, is65c51216al truth table i/o pin mode we cs1 cs2 oe lb ub i/o0-i/o7 i/o8-i/o15 v d d current not selected x h x x x x high-z high-z i s b 1 , i s b 2 x x l x x x high-z high-z i s b 1 , i s b 2 x x x x h h high-z high-z i s b 1 , i s b 2 output disabled h l h h l x high-z high-z i c c h l h h x l high-z high-z i c c read h l h l l h d o u t high-z i c c h l h l h l high-z d o u t h l h l l l d o u t d o u t write l l h x l h d i n high-z i c c l l h x h l high-z d i n l l h x l l d i n d i n operating range (v d d ) range ambient temperature v dd speed commercial 0c to +70c 4.5v - 5.5v 45ns industrial C40c to +85c 4.5v - 5.5v 45ns automotive C40c to +125c 4.5v - 5.5v 55ns capacitance (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 5 pf c o u t output capacitance v o u t = 0v 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v d d = 5.0v.
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00a 02/01/08 is62c51216al, is65c51216al absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.5 to +7.0 v t s t g storage temperature C65 to +150 c p t power dissipation 1.5 w i o u t dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating con - ditions for extended periods may affect reliability. dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C1 ma 2.4 v v o l output low voltage v d d = min., i o l = 2.1 ma 0.4 v v i h input high voltage 2.2 v d d + 0.5 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d com. C1 1 a ind. C2 2 auto. C5 5 i l o output leakage gnd v o u t v d d com. C1 1 a outputs disabled ind. C2 2 auto. C5 5 note: 1. v i l = C3.0v for pulse width less than 10 ns.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. 00a 02/01/08 is62c51216al, is65c51216al ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 480 ? 30 pf including jig and scope 255 ? output 5v 480 ? 5 pf including jig and scope 255 ? output 5v figure 1 figure 2 ac test loads
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00a 02/01/08 is62c51216al, is65c51216al power supply characteristics (1) (over operating range) -45 ns -55 ns symbol parameter test conditions min. max. min. max. unit i c c v d d dynamic operating v d d = max., ce = v i l com. 35 ma supply current i o u t = 0 ma, f = f m a x ind. 40 v i n = v i h or v i l auto. 45 i c c 1 average operating ce = v i l , com. 10 ma current v i n = v i h or v i l , ind. 15 i i/o = 0 ma auto. 20 i s b 1 ttl standby current v d d = max., com. 1 ma (ttl inputs) v i n = v i h or v i l , ce v i h , ind. 1.5 f = 0 auto. 2 i s b 2 cmos standby v d d = max., com. 20 a current (cmos inputs) ce v d d C 0.2v, ind. 40 v i n v d d C 0.2v, auto. 65 or v i n v s s + 0.2v, f = 0 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. 00a 02/01/08 is62c51216al, is65c51216al data valid previous data valid t aa t oha t oha t rc d q0-d15 address ac waveforms read cycle no. 1 (1,2) (address controlled) (cs1 = oe = v i l , cs2 = we = v i h , ub or lb = v i l ) read cycle switching characteristics (1) (over operating range) 45 ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t r c read cycle time 45 55 70 ns t a a address access time 45 55 70 ns t o h a output hold time 10 10 10 ns t a c s 1/ t a c s 2 cs1/cs2 access time 45 55 70 ns t d o e oe access time 20 25 35 ns t h z o e (2) oe to high-z output 15 20 25 ns t l z o e (2) oe to low-z output 5 5 5 ns t h z c s 1/ t h z c s 2 (2) cs1/cs2 to high-z output 0 15 0 20 0 25 ns t l z c s 1/ t l z c s 2 (2) cs1/cs2 to low-z output 10 10 10 ns t b a lb, ub access time 45 55 70 ns t h z b lb, ub to high-z output 0 15 0 20 0 25 ns t l z b lb, ub to low-z output 0 0 0 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v d d -0.2v/0.4v to v d d -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00a 02/01/08 is62c51216al, is65c51216al t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs1 address oe cs1 s cs2 s dout lb s , ub s t hzb t ba t lzb ac waveforms read cycle no. 2 (1,3) ( cs1, cs2, oe, and ub/lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1, ub, or lb = v i l . cs2=we=v i h . 3. address is valid prior to or coincident with cs1 low transition.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. 00a 02/01/08 is62c51216al, is65c51216al notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (cs1) [ (lb) = (ub) ] (we). ac waveforms write cycle no. 1 (1,2) (cs1 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb, ub t pwb write cycle switching characteristics (1,2) (over operating range) 45ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t w c write cycle time 45 55 70 ns t s c s 1/ t s c s 2 cs1/cs2 to write end 35 45 60 ns t a w address setup time to write end 35 45 60 ns t h a address hold from write end 0 0 0 ns t s a address setup time 0 0 0 ns t p w b lb, ub valid to end of write 35 45 60 ns t p w e (4) we pulse width 35 40 50 ns t s d data setup to write end 20 25 30 ns t h d data hold from write end 0 0 0 ns t h z w e (3) we low to high-z output 20 20 30 ns t l z w e (3) we high to low-z output 5 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 4. t p w e > t h z w e + t s d when oe is low.
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00a 02/01/08 is62c51216al, is65c51216al write cycle no. 2 (we controlled: oe is high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. 00a 02/01/08 is62c51216al, is65c51216al write cycle no. 4 (ub/lb controlled) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address cs1 ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps high cs2
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00a 02/01/08 is62c51216al, is65c51216al data retention waveform (cs1 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd 1.65v 1.4v data retention mode data retention switching characteristics (4.5v - 5.5v) symbol parameter test condition min. max. unit v d r v d d for data retention see data retention waveform 2.0 5.5 v i d r data retention current v d d = 2.0v, cs1 v d d C 0.2v 20 a t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns data retention waveform (cs2 controlled) v dd cs2 0.2v t sdr t rdr v dr 0.4v ce2 gnd 3.0 2.2v data retention mode
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. 00a 02/01/08 is62c51216al, is65c51216al industrial range: C40c to +85c speed (ns) order part no. package 45 is62c51216al-45tli tsop-ii, lead-free IS62C51216AL-45MLI mini bga, lead-free (9mmx11mm) is62c51216al (4.5v - 5.5v) industrial range: C40c to +125c speed (ns) order part no. package 55 is65c51216al-55ctla3 tsop-ii, lead-free, copper lead-frame is65c51216al-55mla3 mini bga, lead-free (9mmx11mm) is65c51216al (4.5v - 5.5v)
packaging information integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: m (48-pin) notes: 1. controlling dimensions are in millimeters. seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 mbga - 7.2mm x 8.7mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0 .24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 8.60 8.70 8.80 0.339 0.343 0.346 d1 5.25bsc 0.207bsc e 7.10 7.20 7.30 0.280 0.283 0.287 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 9mm x 11mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0.24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 10.90 11.00 11.10 0.429 0.433 0.437 d1 5.25bsc 0.207bsc e 8.90 9.00 9.10 0.350 0.354 0.358 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 .? ? 0.047 a1 0.25 ? 0.40 0.010 ? 0.016 a2 0.60 ? ? 0.024 ? ? d 7.90 8.00 8.10 0.311 0.314 0.319 d1 5.60bsc 0.220bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 4.00bsc 0.157bsc e 0.80bsc 0.031bsc b 0.40 0.45 0.50 0.016 0.018 0.020 mini ball grid array package code: m (48-pin)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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